Relationship between Vds and Vgs- MOSFET - Electrical Engineering Stack Exchange
the FET functions as a current source with the value of the current set by VGS. The equation of the curve that separates the two regions is VDS = VGS - VGS(off) . If you put 3V on the gate to source then the drain current will be zero until you apply a drain-source voltage (usually via current limiting device. drain current will be proportional to drain voltage (referenced to source voltage ). In this mode the FET.
Electron-flow from the source terminal towards the drain terminal is influenced by an applied voltage. The body simply refers to the bulk of the semiconductor in which the gate, source and drain lie.
Field-effect transistor - Wikipedia
Usually the body terminal is connected to the highest or lowest voltage within the circuit, depending on the type of the FET. The body terminal and the source terminal are sometimes connected together since the source is often connected to the highest or lowest voltage within the circuit, although there are several uses of FETs which do not have such a configuration, such as transmission gates and cascode circuits. Simulation result for right side: Note that the threshold voltage for this device lies around 0.
FET conventional symbol types The FET controls the flow of electrons or electron holes from the source to drain by affecting the size and shape of a "conductive channel" created and influenced by voltage or lack of voltage applied across the gate and source terminals. For simplicity, this discussion assumes that the body and source are connected.
This conductive channel is the "stream" through which electrons flow from source to drain. If the active region expands to completely close the channel, the resistance of the channel from source to drain becomes large, and the FET is effectively turned off like a switch see right figure, when there is very small current.Features of FET
This is called "pinch-off", and the voltage at which it occurs is called the "pinch-off voltage". Conversely, a positive gate-to-source voltage increases the channel size and allows electrons to flow easily see right figure, when there is a conduction channel and current is large.
In an n-channel "enhancement-mode" device, a conductive channel does not exist naturally within the transistor, and a positive gate-to-source voltage is necessary to create one.
The positive voltage attracts free-floating electrons within the body towards the gate, forming a conductive channel. But first, enough electrons must be attracted near the gate to counter the dopant ions added to the body of the FET; this forms a region with no mobile carriers called a depletion regionand the voltage at which this occurs is referred to as the threshold voltage of the FET.
Further gate-to-source voltage increase will attract even more electrons towards the gate which are able to create a conductive channel from source to drain; this process is called inversion. Conversely, in a p-channel "enhancement-mode" device, a conductive region does not exist and negative voltage must be used to generate a conduction channel. In this mode the FET operates like a variable resistor and the FET is said to be operating in a linear mode or ohmic mode. The shape of the inversion region becomes "pinched-off" near the drain end of the channel.
If drain-to-source voltage is increased further, the pinch-off point of the channel begins to move away from the drain towards the source. The FET is said to be in saturation mode;  although some authors refer to it as active mode, for a better analogy with bipolar transistor operating regions. The in-between region is sometimes considered to be part of the ohmic or linear region, even where drain current is not approximately linear with drain voltage.
Even though the conductive channel formed by gate-to-source voltage no longer connects source to drain during saturation mode, carriers are not blocked from flowing.
Considering again an n-channel enhancement-mode device, a depletion region exists in the p-type body, surrounding the conductive channel and drain and source regions.
Chapter 7: MOS Field-Effect-Transistors
Instead the current reaches its maximum value and maintains that value for higher drain-to-source voltages. A depletion layer located at the drain end of the gate accommodates the additional drain-to-source voltage. This behavior is referred to as drain current saturation.
Drain current saturation therefore occurs when the drain-to-source voltage equals the gate-to-source voltage minus the threshold voltage. The value of the saturated drain current, ID,sat. An example is shown in Figure 7. The dotted line separates the quadratic region of operation on the left from the saturation region on the right.
The drain current is still zero if the gate voltage is less than the threshold voltage. However, it is possible to forward bias the drain-bulk p-n junction. A complete circuit model should therefore also include the p-n diodes between the source, the drain and the substrate.
We now use the quadratic model used to calculate some of the small signal parameters, namely the transconductance, gm and the output conductance, gd. The transconductance quantifies the drain current variation with a gate-source voltage variation while keeping the drain-source voltage constant, or: In saturation, the transconductance is constant and equals: Therefore the drain current equals: The measured drain current in saturation is not constant as predicted by the quadratic model.
Instead it increases with drain-source voltage due to channel length modulation, drain induced barrier lowering or two-dimensional field distributions, as discussed in section 7. A simple empirical model, which considers these effects, is given by: The variable depletion layer model Next, we develop the variable depletion layer model, which includes the variation of the charge in the depletion layer between the source and drain.
This variation is caused by the voltage variation along the channel. The inversion layer charge is still given by: We can now apply the linear model to a small section at a distance y from the source and with a thickness dy. This results in the following expression for the drain current, ID: Again, it was assumed that the drain current saturates at its maximum value, since a positive inversion layer charge cannot exist in an n-type MOSFET. The drain voltage at which saturation occurs is given by: Comparison of the quadratic model upper curves and the variable depletion layer model lower curves The figure shows a clear difference between the two models: The transconductance is still given by equation 7.
This equation combined with the saturation voltage equation 7.